发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To expand a write-operation margin while the number of required signal lines for a memory array is being reduced by a method wherein a selection MOSF for write use in the memory cell is made to function as a substantial write means. CONSTITUTION:When a write port in a multiport memory is set to a selection state, an X-word line WXWO for write use or the like is set alternatively to a high level, and a noninverted or inverted signal line for a complementary Y-word line WYMO for write use or the like is set alternatively to the high level. As a result, a memory array, row selection MOSFETs Q13, Q16 for write use in a memory cell MC corresponding to the X-word line for write use at the high level are set to an ON state. In addition, column-selection MOSFETs Q12, Q17 for write use corresponding to the noninverted or inverted Y-word line at the high level are set alternatively to the ON state. Thereby, only one designated cell MC is set alternatively to the selection state, and a write operation according to a piece of input data is executed.
申请公布号 JPH05159576(A) 申请公布日期 1993.06.25
申请号 JP19920135876 申请日期 1992.04.27
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 MIZUKAMI MASAO;SATO YOICHI;SHINAGAWA SATOSHI;NAKANO YUKIO
分类号 G11C11/41;H04Q3/52;H04Q11/04 主分类号 G11C11/41
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