发明名称 POWER-DOWN CIRCUIT AND BIAS CIRCUIT
摘要 PURPOSE:To obtain the technique reducing sufficiently power for a circuit including transistors (TRs) with a low threshold voltage without deteriorating the characteristic of the circuit including the low threshold voltage. CONSTITUTION:A P-channel MOS transistor (TR) M4 whose threshold voltage is comparatively high is provided between a drain and a gate of a MOS TR M2. When the TRM4 is turned off by a control signal PON4x, a current flowing through MOS TRMI is blocked by a MOS TRM3 to reduce the power.
申请公布号 JPH05160704(A) 申请公布日期 1993.06.25
申请号 JP19910349252 申请日期 1991.12.06
申请人 HITACHI LTD 发明人 TANBA HIROKO
分类号 H02J1/00;H03K19/00 主分类号 H02J1/00
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