发明名称 ANORDNING FOER FOERSKJUTNING AV FASEN HOS EN KLOCKSIGNAL SAMT SAETT OCH ANORDNING FOER TAKTAATERVINNING HOS EN DIGITAL DATASIGNAL
摘要 Switching elements (38,40,42,44) have auxiliary clock signal inputs to receive clock signals. A selector circuit (46) receives a control signal from a control signal generator (2), and selects one of the switching elements, allowing one of the clock signals onto a common output (18). The control signal has a variable amplitude and polarity. The selector circuit comprises a logic control circuit, analogue switch and analogue selector which continuously tracks the amplitude and polarity of the control signal to select and activate the control output (48,50,52,54) responsible for switching a switching element.
申请公布号 SE9103833(L) 申请公布日期 1993.06.24
申请号 SE19910003833 申请日期 1991.12.23
申请人 ELLEMTEL UTVECKLINGS AB 发明人 HEDBERG M O J
分类号 H03L7/06;H03K5/13;H03L7/08;H04L7/02;H04L7/033;H04L7/04 主分类号 H03L7/06
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