| 摘要 |
<p>Controller for multiple transfer of data (CTMI) organized by a microprocessor (MPU) between a plurality of memories (SRAM, VRAM), and a computer bus (PSB) comprising a plurality of registers (REGI, REGO) programmed by the microprocessor in order to write information allowing to organize the transfer on a first and second channels, characterized in that the controller is comprised of a central bus (BC, BC1) connected to each register, a first and second channel controllers associated respectively to the first channel and to the second channel, an arbitration device connected on the one hand to the second interface and on the other hand to each of the channel controllers, the arbitration device allocating a given channel to the data paths going to the memories or to the microprocessor, the channel controllers controlling for each channel the writing access of the microprocessor to the registers associated to said channel and the transfer of data to each of said memories. Application to data processing systems.</p> |
