| 摘要 |
A programmable gate array device comprises a substrate having a plurality of cells (50 and 51), each of the cells including at least one semiconductor device (e.g., a transistor) (M1-M4); a first plurality of links or interconnect segments for connecting together selected ones of the semiconductor devices (C, D, E, F, G, H); a second plurality of links or interconnect segments (53, U, V, W, X, Y, Z) and a plurality of connection points, for connecting together selected ones of the first plurality of links to selected ones of the second plurality of links (L1-L26). |
