| 摘要 |
<p>In a differential operational amplifier circuit, having a differential input stage (M1, L1; M2, L2), the output (V1, V2) is made to have zero common mode (V1 + V2 = 0) --i.e., is balanced-- by means of a common mode feedback loop. The loop includes a common mode signal detector (CMSD), connected for detecting common mode (V1 + V2) in the output (V1, V2), and a pair of current steering device (CS1, CS2), connected for drawing equal currents (i) from the respective outputs (I1, I2) of the input stage. During operation, the common mode detector (CMSD) feeds back a suitable control signal (f) to each of the current steering devices, whereby the currents (i) are adjusted to suppress the common mode (V1 + V2) in the output (V1, V2).</p> |
