| 摘要 |
The double edge trigger RS flip-flop inputs data synchronized to double edge of clock signal so that data input speed is increased. Two input signals (S,R) are applied to gates of P-MOS transistors (P1,P2,P10,P11) and N-MOS transistors (N1,N3,N9,N10) and clock pulses are applied to gates of P-MOS transistors (P3,P6) and N-MOS transistors (N6,N11). Vcc is applied to drains of P-MOS transistors (P1,P2,P6). Sources of P-MOS transistors (P1,P2) are connected to the gate of transistor (P3).
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