| 摘要 |
<p>Controller for multiple data transfers (CTMI) organised by a microprocessor (MPU) between a plurality of memories (SRAM, VRAM), and a computer bus (PSB) comprising a plurality of registers (REGI, REGO) programmed by the microprocessor in order to write therein information allowing organisation of the transfer over a first and a second channel, characterised in that it comprises - a central bus (BC, BC1) connected to each of the registers - a first and a second channel controller, associated respectively with the first and second channel, - an arbitration device connected, on one hand, to the second interface and, on the other hand, to each of the channel controllers. The arbitration device allocating a given channel to the data paths going to the memories or the microprocessor, the channel controllers controlling, for each channel, write access by the microprocessor to the registers associated with this channel and the transfer of the data to each of the said memories. Applicable to computer systems. <IMAGE></p> |
