Pseudo logarithmic analog step adder

摘要

A signal to be scaled is supplied to three parallel amplifiers with gains of 0.1, 1, and 10, which each amplify the input simultaneously. The amplifiers are designed so that their output is limited to 1 volt regardless of the level of voltage at their input. This allows the lower magnitude portions of the signals to be amplified without amplifying the higher magnitude signals. The output of the amplifiers are summed together to provide the scaled signal.