| 摘要 |
<p>PURPOSE:To execute the asynchronous reading and writing operations of a synchronizing dual port RAM by a CPU. CONSTITUTION:An interface circuit 10 of a synchronizing dual port RAM 30 and a CPU 20 consists of an address latch circuit for the RAM 30, a write data latch circuit, a read data buffer circuit, a data writing mode flag generating circuit, a flag generating circuit which shows a fact that the data to be read are valid, a flag reading buffer circuit, the generating circuits which produce the chip selection signal, the write enable signal, and the output enable signal to the RAM 30, and a program which secures the flag read/read-out/write timing through the buffer circuits.</p> |
