| 摘要 |
PURPOSE:To enable efficient data transfer by efficiently using each bus on the digital signal processor performing the high-speed four rules operation. CONSTITUTION:The signal processor is provided with a first arithmetic means performing calculation based on plural digital signal data, a first bus 16 connected to the first arithmetic means, a second arithmetic means performing the operation based on the plural digital signal data, a second bus 26 connected to the second arithmetic means, and a bus connection means provided between the first bus 16 and the second bus 26 and connecting the first and second three-state buffers 41 and 42 reversely in parallel. |
