| 摘要 |
PURPOSE:To provide the division unit realizing the higher processing speed with small circuitry without using a normal digital multiplier having the slower processing speed with large scale circuitry. CONSTITUTION:After providing a value multiplying a divisor by a prediction of the first quotient by shifting a divider leftward by-2 (digit number of the number to be divided) with a shift register 1, the smaller value is estimated as the quotient when the number to be divided is smaller than the output of an adder 3 and when it is larger, the larger number is estimated as the quotient and the processing is repeated until the output of the adder 3 and the number to be divided become equal in the comparison by a comparator 4. |
