| 摘要 |
PURPOSE:To reduce power consumption by reducing a lockup time at application of power to the PLL circuit or a frequency division data revision. CONSTITUTION:When frequency division data are applied by a control signal CE, a voltage based on the frequency division data is generated by a D/A converter circuit 11 and since a timing generating circuit 13 closes a switch 12 simultaneously, its oscillating frequency of a VCO 2 is controlled by an output voltage of the D/A converter circuit 11 and the frequency is controlled to be a frequency set quickly by the frequency division data. Then when a switch 12 is opened by an output of the timing generating circuit 13 after a prescribed time, an output of an LPF 4 controls the VCO 2 to make the phase difference between the frequency division outputs fP and fR coincident. |
