| 摘要 |
PURPOSE:To shorten a synchronization pull-in time even when a frame synchro nizing pattern is an alternation by supplying the logical sum result of plural synchronization detection protecting parts to a flip flip (FF). CONSTITUTION:The compared matching of the comparison pattern of a positive logical operation prepared based on a frame pulse indicating the head of received data by a first frame pattern preparing part 4-1, with the received data, is detected. Then, the continuous plural number of times of matching with the frame pattern is detected by a synchronization detection protecting part 2-1 based on the matched result, and an initialization signal is outputted In the same way, the compared matching of the comparison pattern of the negative logical operation prepared by a second frame pattern preparing part 4-2 based on the frame pulse indicating the head of the received data, with the received data, is detected. Then, the continuous plural number of times of matching with the frame pattern is detected by a synchronization detection protecting part 2-2 based on the matched result, and the initialization signal is outputted. Then, the logical sum result of the protecting parts 2-1 and 2-2 is added to an FF 3, so that a synchronization establishment detection and a synchronization disconnection detection can be attained. |
