| 摘要 |
<p>PURPOSE:To obtain the shared memory control circuit which enables access from another normally operable CPU to a memory cell even when an operating clock is stopped. CONSTITUTION:Normally, a first-order access signal S7 is generated corresponding to an access request from a shared memory arbitration part 91 and when a first-order clock S1 is stopped, a second-order access signal S9 is generated corresponding to an access request from a second-order CPU. Then, the access control of the memory cell is executed by selecting one of those signals according to a detecting signal S8 for the clock stop, and the first-order clock S1 and a second-order clock S2 are switched corresponding to the detecting signal S8 for the clock stop. According to the selected clock, an access signal S5 is generated corresponding to the access request from the shared memory arbitration part 91 or the access request from the second-order CPU, and the access control of the memory cell is executed.</p> |
