Data transfer circuit for integrated circuit test appts. - has masking circuit between test system and hardware to maintain transfer with different clock rates

摘要

The integrated circuit test system includes a host system microprocessor (1) operating with a limited clock speed an a monitoring hardware unit (2) operating at high clock rate. The processor delivers signals to a register (3) via an address bus (101), data bus (102), read/write control (103a) and a chip select line (103b). The lines connect with a register that acts as a buffer between the two units. A cycle control unit (4) generates mask and load signals handled as a gating circuit (50). ADVANTAGE - Provides reliable transfer between different clock rate systems.