发明名称 |
CONTINUOUS RECEIVER CLOCK ALIGNMENT AND EQUALIZATION OPTIMIZATION |
摘要 |
The available bandwidth of an Input/Output (I/O) communications link is increased by removing the need for retraining events on a communications link. This results in removing a potentially severe system performance degradation penalty that may occur from data traffic stoppage during the retraining events. The available bandwidth is further increased by removing a timing error which results in increasing a timing margin for other components. This results in an increase in the maximum speed of systems with high speed I/O and communication transceiver Integrated Circuits (IC)s.
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申请公布号 |
US2009154626(A1) |
申请公布日期 |
2009.06.18 |
申请号 |
US20070957451 |
申请日期 |
2007.12.15 |
申请人 |
ANDERSON WARREN R;BECKER MATTHEW E |
发明人 |
ANDERSON WARREN R.;BECKER MATTHEW E. |
分类号 |
H04L7/02 |
主分类号 |
H04L7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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