发明名称 DYNAMIC INSPECTING METHOD FOR DIGITAL LOGIC CIRCUIT
摘要 PURPOSE: To guarantee the unitary corresponding relation of input and output bit patterns by inserting a vacant cycle of no change at an input signal after two or more predetermined number of inspecting cycles. CONSTITUTION: When a vacant (non-operating) cycle L having characteristics of no longer change occurrence is inserted in input signals RZ, RTO, NRZ after two or more predetermined number (n) of inspecting cycles, sufficient time for responding (rising vibration) i given to a logic circuit, and the output is evaluated only at the time of finishing the cycle L. For example, when the cycle L group is inserted after the four inspection cycles at an RZ signal, it is masked (mark 'x') except the last cycle L (upward arrow), and one time strobe (evaluation) can be performed by the four time executions of the test pattern after the respective cycles. Since the cycle L is distributed over the whole bit pattern in the fixed array, the masking can be very simply conducted.
申请公布号 JPH05142303(A) 申请公布日期 1993.06.08
申请号 JP19910193816 申请日期 1991.08.02
申请人 SIEMENS AG 发明人 KAARU TORAUPU
分类号 G01R31/3183;G01R31/3193;G06F11/22;G06F17/50 主分类号 G01R31/3183
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