BICMOS OUTPUT BUFFER CIRCUIT WITH CMOS DATA PATHS AND BIPOLAR CURRENT AMPLIFICATION

摘要

Attorney Docket No. NS18698 BICMOS OUTPUT BUFFER CIRCUIT WITH CMOS DATA PATHS /A BIPOLAR CURRENT AMPLIFICATION A BICMOS output buffer circuit incorporating CMOS transistors and bipolar transistors is coupled between high and low potential power rails (VCCI,GNDO) for delivering output signals of high and low potential levels at an output (VOUT). A bipolar output stage is formed by relatively large current conducting bipolar output pullup (Q24,Q22) and pulldown (Q44) transistors coupled to the output (VOUT) and provides relatively low output impedance. Data signal paths coupled to the output stage are defined by CMOS transistors including CMOS input stages coupled to the input (VIN). Small current conducting CMOS transistors afford relatively high input impedance. The bipolar output stage provides current amplification of data signals from the CMOS transistor defined data signal paths. The P channel and N channel CMOS transistors of a pullup predriver input stage (Q15,Q14) are constructed with the P/N ratio of channel width dimensions skewed relative to the P/ ratio of channel width dimensions of respective P channel and N channel CMOS transistors of the pulldown predriver input stage (Q11,Q10) for skewing the input threshold voltage levels of the respective pullup and pulldown predriver input stages. The skewed construction minimizes simultaneous conduction between the bipolar output pullup transistor (Q22) and pulldown transistor (Q24). A pulldown driver stage (Q60,Q9A) coupled to a base node of the bipolar output pulldown transistor (Q44), includes a CMOS phase splitting pulldown driver transistor (Q60) and a fast CMOS Miller Killer (MK) transistor (Q9A) which functions as both DCMK and ACMK transistor.