POWER DOWN MILLER KILLER CIRCUIT

摘要

POWER DOWN MILLER KILLER CIRCUIT A circuit to be used with bistate and tristate output buffers as a means of diverting from an output pulldown transistor the Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a CMOS transistor, PDMK transistor (Q99), coupled between the output pulldown transistor and the low-potential power rail of the output buffer. The PDMK transistor (Q99) is controlled by a PDMK driver transistor (Q99A) coupled to the buffer output VOUT. The PDMK driver transistor (Q99A) is controlled by the output buffer's high-potential power rail and so turns on the PDMK transistor (Q99) only when the buffer is powered down. The invention also encompasses a PDMK disabler transistor (Q98) coupled to the data input VIN to ensure that the PDMK transistor (Q99) never pulls the control node of the output pulldown transistor when the buffer is in its active low state.