| 摘要 |
A very large memory structure in which the extent and capacitive loading of global buses are reduced by an arrangement in which global data, address and control buses are connected to column buses through a column disable block for each column of memory modules. The column disable blocks also provide for selection of only a subset of data lines for connection between the global data bus and an associated column data bus. Further, a column disable register in each column disable block permits output from the column data bus to be selectively ignored on the basis of bit position. The column disable registers are uniquely addressable by column, for the selective disablement of column data bus lines. In the described embodiment of the invention, the global buses are triply redundant and the column disable blocks also include voting circuitry for processing of signals from the global buses. |
