发明名称 SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD
摘要 PURPOSE:To reduce resistance between a transistor region and a polycrystalline layer, i.e., a storage node of a capacitor, by forming an epitaxial layer as a whole together with a polycrystalline layer that covers an insulating layer on a trench inside wall. CONSTITUTION:An accumulated electrode (a polycrystalline silicon film 34) within a groove 15 and a single-crystal silicon film 33 on an active region are selectively formed at the same time under reduced pressure continuously in a chemical vapor deposition method. Since a sidewall contact is unnecessary in this method, a spontaneous oxide film can be eliminated at an interface between the accumulated electrode and a source or drain in a transistor region 13. Consequently, resistance between a transistor region and a polycrystalline layer, i.e., a storage node of the capacitor, can be reduced.
申请公布号 JPH05136365(A) 申请公布日期 1993.06.01
申请号 JP19920120454 申请日期 1992.05.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUO NAOTO;OGAWA HISASHI;NAKADA YOSHIRO;OKADA SHOZO
分类号 H01L21/76;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108 主分类号 H01L21/76
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