| 摘要 |
A memory testing system for an electronic computing system includes multiple memory modules, each equipped with error detecting and correcting (EDC) circuitry, and is operable in a diagnostic test mode wherein read and write tests of the modules are performed in parallel. Each module includes a command/status register (CSR), used in identifying errors occurring in that module by capturing various signals at the time of the error. These signals include the type of error, the memory address involved in the error, the check bits of the data associated with the error, and the syndromes of the data. After pre-setting each CSR's diagnostic register, one module operates in a "target" mode, and the remaining modules operate in a "shadow" mode. The target module operates normally during read and write operations. When the target module is directed to write data to a particular address, the shadow modules write the same data to corresponding addresses in their memory banks. When the target module is given a read command, the shadow modules read data from the corresponding addresses of their memory banks; however, the shadow modules do not place this data on the CPU bus. By polling the CSRs, the CPU can obtain detailed information regarding memory errors, such as the type and cause of the errors, and the identity of the module where the errors occurred.
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