发明名称 Grounding dummy gate in scaled layout design
摘要 A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.
申请公布号 US9379058(B2) 申请公布日期 2016.06.28
申请号 US201414274184 申请日期 2014.05.09
申请人 QUALCOMM INCORPORATED 发明人 Song Stanley Seungchul;Wang Zhongze;Kwon Ohsang;Rim Kern;Zhu John Jianhong;Chen Xiangdong;Vang Foua;Stephany Raymond George;Yeap Choh Fei
分类号 H01L29/423;H01L29/417;H01L23/528;H01L23/522;H01L27/088;H01L21/768;H01L27/118 主分类号 H01L29/423
代理机构 Seyfarth Shaw LLP 代理人 Seyfarth Shaw LLP
主权项 1. A semiconductor device, comprising: a dummy gate in a semiconductor device active area; a first active contact adjacent to the dummy gate; a first stacked contact electrically coupled to the first active contact and including a first isolation layer on sidewalls electrically isolating the first stacked contact from the dummy gate and a cap layer on a surface of the first stacked contact opposite the first active contact; and a first via electrically coupled to the dummy gate and landing directly on the surface of the first stacked contact through a portion of the cap layer and directly contacting the first isolating layer on a sidewall of the first stacked contact, the first via arranged to electrically couple the first stacked contact and the first active contact to the dummy gate to ground the dummy gate.
地址 San Diego CA US