发明名称 |
Method and structure for improved floating gate oxide integrity in floating gate semiconductor devices |
摘要 |
Methods for forming floating gate transistors provide for using a self-aligned plug formed over a floating gate electrode without use of an additional photolithography operation. The plug is centrally disposed and is formed and aligned using spacers. The spacers are formed alongside edges of a patterned sacrificial, oxidation resistant layer that includes an opening that defines the floating gate region. The plug may be formed of a silicon material and which becomes oxidized along with the floating gate such that the plug eventually forms part of the floating gate electrode or the plug may be formed of a nitride or other oxidation resistant material to retard or prevent oxidation in the central portion of the floating gate in which the plug is aligned. |
申请公布号 |
US9378960(B2) |
申请公布日期 |
2016.06.28 |
申请号 |
US201113092043 |
申请日期 |
2011.04.21 |
申请人 |
WAFERTECH, LLC |
发明人 |
Wey Yihguei |
分类号 |
H01L21/336;H01L21/28;H01L29/423 |
主分类号 |
H01L21/336 |
代理机构 |
Duane Morris LLP |
代理人 |
Duane Morris LLP |
主权项 |
1. A method for forming a floating gate transistor comprising:
forming a silicon layer over a substrate; forming a patterned nitride layer over said silicon layer, said patterned nitride layer including an opening therein defining a floating gate region of a floating gate transistor; forming a plug on a top surface of, and directly contacting said silicon layer in said floating gate region without use of a photomask; and thermally oxidizing, wherein said plug comprises a silicon plug and said thermally oxidizing comprises oxidizing said silicon plug and said silicon layer in said floating gate region such that an oxide layer is formed and, after said thermal oxidation, silicon thickness in a central portion of said floating gate region is greater than silicon thickness at outer portions of said floating gate region. |
地址 |
Camas WA US |