| 摘要 |
PURPOSE:To suppress noise by providing a first pulse generating circuit generating a pulse having predetermined width and a second pulse generating circuit generating a pulse having period shorter than the width of pulse generated from the first pulse generating circuit thereby producing a pulse signal comprising a second pulse and a first pulse following thereto. CONSTITUTION:When a data '1, 0, 0, 0' is applied on a data bus DB2, a register D8 takes in '1' and registers D, D10, D11 take in '0', respectively. A timer T4 measures a time shorter than that of a timer T5 repeatedly and thus measured time is inputted to the third input terminal of an AND circuit Alb. Flug F2 is provided with '1'. In other words, the register D8 takes in data or '1' and delivers pulse signals intermittently to a real time port RTPO0 during an interval from rising of the signal to the end of time measurement of jug timer T5 and stops intermittent delivery at the end of time measurement of the timer T5 to begin delivery of square pulse signals. |
