| 摘要 |
PURPOSE:To prevent the occurrence of a 2-bit error by reading out an address error occurrence detection bit together with the data to decide the first occurrence or the second and subsequent occurrence of the 1-bit errors and producing an interruption signal to report a fact that the 1-bit faults occurred twice in the same address. CONSTITUTION:The error occurrence detection bits of the same address are read out together with the data so as to decide the first occurrence of the second or the subsequent and subsequent occurrence of the 1-bit errors while a program is working. Then an interruption signal is produced to report a fact that the 1-bit errors occur twice in the same address of a memory 3 to a CPU 1. The negative logic value is set to the error occurrence detection bit in an initialization routine set after application of a power supply. The data and the check bit of the memory 3 are corrected when the error occurrence detection bit is equal to the negative logic value. At the same time, the error occurrence detection bits of the same address are written in the positive logic values. |
