Semiconductor device having a pad array carrier package

摘要

A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.