发明名称 Method for forming a three-dimensional structure of metal-insulator-metal type
摘要 A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.
申请公布号 US9391015(B2) 申请公布日期 2016.07.12
申请号 US201314079393 申请日期 2013.11.13
申请人 STMICROELECTRONICS S.A.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Jeannot Simon;Tannhof Pascal
分类号 H01L21/02;H01L23/522;H01L49/02 主分类号 H01L21/02
代理机构 Seed IP Law Group PLLC 代理人 Seed IP Law Group PLLC
主权项 1. An electronic device, comprising: a stack of interconnection levels, each interconnection level including a plurality of vias and a plurality of conductive tracks, a first interconnection level of the stack of interconnection levels including: a first conductive track;a trench formed in the first conductive track, the trench being surrounded by the first conductive track;a capacitor formed in the trench, the capacitor including a conformal first electrode formed in the trench and in contact with internal walls of the first conductive track, a conformal insulating layer formed on the first electrode and in the trench, and a conformal second electrode formed on the insulating layer and in the trench, the first electrode being distinct from the first conductive track, the first electrode having side surfaces that are completely and laterally surrounded by the first conductive track, the insulating layer being formed between the first electrode and the second electrode; anda conductive material formed in the trench and in contact with the second electrode, wherein the capacitor and conductive material fill the trench.
地址 Montrouge FR