发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To improve multiplication precision remarkably with a simple constitution by shifting the 2nd input signal in phase from the 1st input signal by a fixed value. CONSTITUTION:The 1st input signal Vi1 is input to integrator 2 by way of switch 1a. Reference signals Vr and -Vr are also input to integrator 2 selectively through switches 1b and 1c. The output of integrator 2 is input to comparator 3. This comparator 3, when the output of integrator 2 is greater than a comparison reference level, generates a signal of level H, which is supplied to switch control circuit 4 to perform pulse-width modulation that corresponds to signal Vi1. Input signal Vr2, on the other hand, is phase-delayed through phase circuit 6 and then input to integrator 7 through switch 5 turned on-off with the output of circuit 4. This integra- tor 7 outputs the products of signals Vr1 and Vr2. Thus, signal Vr2 is delayed by a certain time width to eliminate equivalently sampling time difference from signals Vr1 and Vr2, so that a high-precision arithmetic value can be obtained.
申请公布号 JPS5617472(A) 申请公布日期 1981.02.19
申请号 JP19790093974 申请日期 1979.07.24
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SUGIYAMA FUMIO;TASHIRO ISAO
分类号 G06G7/161 主分类号 G06G7/161
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