| 摘要 |
<p>A receiving buffer control system comprises a memory (4) having a buffer area (8) serving as a receiving buffer, data being applied to the memory via a bus, a write pointer (11) indicating a write address of the buffer area, and a read pointer (12) indicating a read address of the buffer area. An overrun/underrun detection circuit (17) detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part (9) disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation. <IMAGE></p> |
