| 摘要 |
<p>A register read control method for use with an information processing apparatus for executing a plurality of instructions in parallel during pipeline processing. The apparatus comprises a register file (REG), a register designation selector (IR), a cache register (OP11-OP22), a selector (SEL11-SEL22), an arithmetic circuit (ALU1, ALU2), a register cache pass (RCPS1, RCPS2) and a comparator (COMP). When the comparator (COMP) detects a coincidence between the data in the cache register (OP11-OP22) for the current instruction and the operand in the next instruction, the comparator (COMP) causes the selector (SEL11-SEL22) to select the register cache pass (RCPS1, RCPS2) as input thereto and to move the contents of the cache register (OP11-OP22) back directly to the cache register (OP11-OP22) via the register cache pass (RCPS1, RCPS2). <IMAGE></p> |
