发明名称
摘要 PURPOSE:To reduce the load of data processing based upon a processor by shifting digital data in plural ranges (conversion ranges) obtained from an A/D converter to a prescribed direction by the number of bits corresponding to the ranges and then inputting the shifted data to the processor. CONSTITUTION:An analog signal 1 is inputted to the A/D converter 3 and the converted parallel digital signal 2 and converted unit information 5 are outputted. The signal 2 is set up in a register 6 in a data conversion part 14. The information 5 is inputted to a shift pulse generating part 8 and shift pulses P corresponding to the conversion unit are outputted. Consequently, the data in the register 6 are shifted by the number of the shift pulses P and complement information F outputted from a complement generating part 15 is set up in the register 6. Thus, the value of the analog signal 1 is found out by the processor 4 on the basis of the product of the shifted digital information 9 and the number of shift pulses P.
申请公布号 JPH0535451(B2) 申请公布日期 1993.05.26
申请号 JP19850157191 申请日期 1985.07.17
申请人 FUJI FACOM CORP 发明人 NISHOKO TAKAO
分类号 G06F3/05;G06F7/00;G06F7/76 主分类号 G06F3/05
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