| 摘要 |
PROBLEM TO BE SOLVED: To provide a DMA controller that completes data transfer associated with processing of high priority in an as short time as possible, and has small variance in transfer time.SOLUTION: A DMA controller according to the present invention comprises: a plurality of transfer request generation parts which report transfer requests according to transfer request setting information; a scheduler which receives the transfer requests from the plurality of transfer request generation parts, schedules the transfer requests based upon priority order setting information, and selects and reports one transfer setting number as an object of execution based upon a scheduling result; and a DMA transfer execution part which reads out transfer setting information corresponding to the transfer setting number reported from the scheduler and executes DMA transfer. The transfer request setting information includes a precedent wait time, the transfer request generation part gives notice of a wait request to the scheduler based upon the precedent wait time precedently to the transfer request, and the scheduler gives wait notice to the DMA transfer execution part, so that data transfer of low priority can be inhibited in advance.SELECTED DRAWING: Figure 1 |
