发明名称 Memory access device for accessing memory cell array diagonally
摘要 A memory cell array stores data in its row and column directions. A counter counts clock signal pulses, represents the counted value by using binary system, and outputs, as the column address, values occupying predetermined lower bit positions, while supplying values occupying predetermined upper and lower bit positions into an adder circuit. The adder circuit processes the values supplied, and outputs, as the row address, the values thus processed, so that the memory cell array is accessed diagonally.
申请公布号 US5214611(A) 申请公布日期 1993.05.25
申请号 US19910682241 申请日期 1991.04.09
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIGEHARA, HIROSHI;KAWAAI, TOSHIMASA
分类号 G06F12/16;G06F12/02;G11C8/04;G11C29/00 主分类号 G06F12/16
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