发明名称 INFORMATION TRANSMITTER
摘要 PURPOSE:To prevent out of synchronism and switching from giving effect onto a post-stage by delaying an out of synchronism detection signal being an output of an out of synchronism detection means with a 1st delay means. CONSTITUTION:An out of synchronism detection circuit 17g detects out of synchronism of an output signal from a buffer memory 17b and gives an out of synchronism detection signal to a switch 17c via a delay circuit 17i when out of synchronism takes place. The delay circuit 17i delays the out of synchronism detection signal and gives the delayed signal to the switch 17c. Moreover, a delay time of the delay circuit 17i is selected to be a time enough for matching the synchronization of a blue signal. Moreover, when the synchronization of the output signal of the buffer memory 17c is matched during the delay, the delay circuit 17i outputs no out of synchronism detection signal. A blue signal from a blue signal generator 17f is given to the switch l7c in addition to the output signal of the buffer memory l7b.
申请公布号 JPH05130092(A) 申请公布日期 1993.05.25
申请号 JP19910293345 申请日期 1991.11.08
申请人 FUJITSU LTD 发明人 HIGUCHI SHIGENOBU
分类号 H04L7/00 主分类号 H04L7/00
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