| 摘要 |
PURPOSE:To realize the fast data reading by the low consumption current. CONSTITUTION:MOS transistors Q20 and Q21 to divide reading exclusive-use data line pairs RI and /RI into first parts NO1 and NO2 and second parts NOA and NOB and receive the prescribed reference potential Vref to the gate are provided at the first and second parts. To the first parts, a current supply load circuit 8 of an amplifier 7 for reading and an output node only are connected. To the second parts, a driving circuit 9 provided at plural bit line pairs of the memory cell array is commonly coupled. By the transistors Q20 and Q21, the capacity of the first parts and the second parts is separated, the parasitic capacity incidental to the output node can be reduced and the reading action can be fast realized. By the transistors Q20 and Q21, the logical amplitude of the second parts is limited, the charging discharging current of the gate capacity incidental to the second parts can be reduced and the low consumption current can be realized. |
