发明名称 DEFECT RELIEF METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS EXECUTION EQUIPMENT
摘要 <p>PURPOSE:To reduce failures at the time of burying a circuit block for defect relief, and improve the yield in the manufacturing process of a semiconductor integrated circuit device. CONSTITUTION:In a region where an imperfect circuit block 3B on a substrate 1 is eliminated, a circuit block 3B' for defect relief wherein a magnetic layer 13 is formed on the rear is arranged. While a magnetic field is applied to the circuit block 3B' for defect relief its arrangement position is determined for at least one out of a plurality of circuit blocks 3A, 3C on the main surface of the substrate 1. In the state where the arrangement position is determined, the circuit block 3B' for defect recovery is fixed to the substrate 1.</p>
申请公布号 JPH05129419(A) 申请公布日期 1993.05.25
申请号 JP19910287633 申请日期 1991.11.01
申请人 HITACHI LTD 发明人 USAMI MITSUO
分类号 H01L21/66;H01L21/68;H01L21/82 主分类号 H01L21/66
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