| 摘要 |
PURPOSE:To provide a semiconductor memory device in which high integration can be realized even when memory cells are arranged in lateral. CONSTITUTION:Polycrystalline silicon layers (word lines) 4 and N-type embedded diffusion layers (bit lines) 6 are arranged, at same intervals, on a P-type semiconductor substrate 2. The N-type embedded diffusion layers 6 are isolsted from the word lines 4 through isolation films 8. Channel length of cell transistor constituting each bit is defined by the interval of adjacent N-type embedded diffusion layer 6 and the direction of channel is aligned with that of the word line. Drain and source of memory cell juxtaposed in the direction of the word line are connected, respectively, with first and second bit lines. In practice, drain diffusion layer and source diffusion layer of each cell, transistor are used, respectively, as the first and second bit lines. |
