| 摘要 |
A data latch circuit of a delta sigma modulator is controlled in timing of data output by clock signal. For this purpose, the data latch circuit has a reverse phase clock input terminal connected to a first delay circuit and a forward phase clock input terminal connected to a second delay circuit. The latch circuit is composed of two P-MOS transistors and two N-MOS transistors. The delay times of the first and second delay circuits are coincided, and those of the respective two P- and N-MOS transistors are also coincided.
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