| 摘要 |
PURPOSE:To automatize not only free-run frequency adjustment but also correction of data discrimination point deviation by comparing the phase, of the free-run frequency of a first PLL circuit for clock reproducing with that of a reference frequency and feeding back the phase error to the first PLL circuit by means of a second PLL circuit to equalize these two frequencies. CONSTITUTION:In the case of adjustment of the free-run frequency in a PLL circuit, the input of a control signal input terminal 22 is set to '1', and the output of a 3-state buffer 17 is set to a high impedance, and the central DC voltage of a triangular wave signal is outputted from a band limiting circuit 18, and phase comparison is not performed in the first PLL circuit, and the second PLL circuit is operated. Frequency dividers 25, 26 take the output signal of a VCO 8 and that of a reference signal source 23 as inputs respectively and divide their frequencies, and their phases are compared with each other by a phase comparator 27, and the error signal has the band limited by a second loop filter 28 and is inputted to am operational amplifier 7, thus constituting a second PLL. After this synchronization, the terminal 22 is switched to '0' to switch the input of the frequency divider 25 to the reference signal, and a desired frequency division ratio is set. |
