| 摘要 |
PURPOSE:To prevent erroneous operation due to wiring delay, etc., by connecting the output of a first FF to the input of a second FF via a gate means, inputting a first clock in the clock input of the first FF and in the control input of the gate means and inputting a second clock in the clock input of the second FF respectively. CONSTITUTION:Synchronously with the rising edge of the clock signal CLK1 of time t1, an input signal I is latched by FF1, when the propagation of the signal I from a node N1 to a node N2 is inhibited by the gate means 10. Synchronously with the falling edge of the next signal CLK1, the inhibition of the signal propagation is released by the means 10, and the signal I is transferred to the node N2. This time, assuming the difference of rising time between the signal CLK1 and 2 as TS, is after t1+TS. Consequently, by the rising edge of the signal CLK2 of the time t1+TS, the data that is transferred to the node N2 is not transferred to the output O of FF2. Thus, when a clock skew is generated due to wiring delay, etc., erroneous operations are prevented. |
