VARIABLE DELAY CIRCUIT WITH VERY SMALL DELAY

摘要

PURPOSE:To provide a variable delay quantity with high resolution. CONSTITUTION:A buffer 17 having an output impedance of a proper quantity and outputting a logic level is connected to a delay input terminal 15, a Schmitt trigger buffer 18 is connected to an output of the buffer 17 and an output of the buffer 18 is connected to a delay output terminal 16. An input of a CMOS 21 is connected to a connecting point 19 of the buffers 17, 18, a drain and a source of the CMOS 21 are connected respectively to a power supply terminal 24 and ground through MOSFETs 22, 23 respectively. A selection signal input terminal 25 is connected directly to a gate of a FET 22 and to a gate of a FET 23 via an inverter 26. When the FETs 22, 23 are both turned off, an input signal at the input terminal 15 is outputted to the output terminal 16 with a very small delay, and when the FETs 22, 23 are both turned on, the CMOS 21 acts like an inverter, and a signal at the output terminal 16 is delayed due to a delay of the mirror effect by the switching capacitance and an output impedance at the switching of the buffer 17. A delay proportional to number of CMOS in the inverter operation connecting to the connecting point 19 is obtained.