| 摘要 |
Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. A PIN diode region 14 of the first conductivity type is then implanted in the substrate 10 at the first surface and spaced from the HBT subcollector region 12. Next, an i-layer 16 is grown over the first surface. Next, an HBT base/PIN diode layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12 and the PIN diode region 14. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base/PIN diode layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base/PIN diode layer 22. Afterwards, an isolation region 30 is implanted at the boundary between the HBT subcollector region 12 and the PIN diode region 14, the isolation region 30 extending down into the substrate 10. Next, the HBT emitter layer 24/26/28 is etched away over the PIN diode region 14. Lastly, conductive contacts 32, 36, 40, 38 and 42 are formed to the HBT emitter layer 24/26/28, the HBT base layer 22, the HBT subcollector region 12, the PIN diode layer 22 and the PIN diode region 14.
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