| 发明名称 |
System and method of interfacing co-processors and input/output devices via a main memory system |
| 摘要 |
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. |
| 申请公布号 |
US9444495(B2) |
申请公布日期 |
2016.09.13 |
| 申请号 |
US201514635960 |
申请日期 |
2015.03.02 |
| 申请人 |
DIABLO TECHNOLOGIES INC. |
发明人 |
Takefman Michael L.;Amer Maher;Badalone Riccardo |
| 分类号 |
G06F11/00;H03M13/00;H03M13/27;H03M13/05;G06F11/10;G06F12/02;G06F12/06;G06F13/20;H04L9/06;G06F9/44;G06F13/42 |
主分类号 |
G06F11/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A device comprising:
a processing unit; an I/O interface configured to communicate with a co-processing unit or input/output device; a host interface configured to communicate with a host memory controller of a host system over a memory bus; and a data de-interleaver configured to:
determine an interleaving mapping of the host memory controller; andgenerate de-interleaved data from bit-interleaved data received from the host memory controller. |
| 地址 |
Ottawa CA |
