FEHLERBESEITIGUNGSSYSTEM IN EINEM DATENPROZESSOR MIT EINEM STEUERSPEICHER.
摘要
An error recovery system in a data processor of the pipeline type, including control storage for storing instruction data, having an error correction and detection code adapted to the detection and correction of errors, for controlling the data processor. A parity check circuit checks instructions read from the control storage and stops at least a part of pipeline processing immediately upon the detection of an error. An error correction circuit corrects the error in the read instruction data and rewrites the instruction data into the control storage while the part of the pipeline processing is stopped.
申请公布号
DE3587058(T2)
申请公布日期
1993.05.19
申请号
DE19853587058T
申请日期
1985.08.15
申请人
FUJITSU LTD., KAWASAKI, KANAGAWA, JP
发明人
KITAMURA, TOSHIAKI, OTA-KU TOKYO 146, JP;OINAGA, YUJI, SETAGAYA-KU TOKYO 154, JP