| 摘要 |
<p>A detector circuit (2), preferably for an integrated circuit tester, compares an unknown binary signal (A) with two reference voltages (Vr1, Vr2). The outputs of comparators (5, 6) are fed to a 1-of-n decoder (11) whose outputs (12-14) are, in turn, fed to latch circuits (22-24). Those latch circuits comprise a feedback loop which is activated by a control signal (G) such that they may be operated either in a transmission mode or in a mode wherein all states of the unknown binary signal A during a prescribed time window may be recorded. The outputs (K,M,O) of latch circuits (22-24) are fed to D flip-flops (38-40), in order to sample the outputs of the latch circuits (22-24). <IMAGE></p> |
