发明名称 N-STAGE JITTER ABSORBING CIRCUIT
摘要 <p>PURPOSE:To eliminate the occurrence of an error by selecting the Q of a tank circuit to be higher as a circuit receiving an output of a flip-flop as an input is connected by n-stages so as to absorb jitter of a signal of a transmission line. CONSTITUTION:n-Stages of circuits each comprising flip-flops F1-Fn receiving a signal including jitter on a transmission line and outputting an NRZ signal, tank circuits T1-Tn receiving the signal on the transmission line to extract a clock and outputting their outputs to the flip-flops and a circuit receiving an output of the flip-flops F1-Fn are connected in cascade. However, the Q1 of the 1st stage tank circuit is selected to segment the expected input jitter without mistake, the Q2 of the 2nd stage tank circuit is selected to be higher than the Q1 so as to segment an output of the flip-flop of the pre-stage without any error. Thin the Qn of the n-th stage flip-flop is selected so as to have no high frequency jitter at its output. Thus, the jitter of the signal on the transmission line is absorbed by using the n-stage jitter absorbing circuits.</p>
申请公布号 JPH05122207(A) 申请公布日期 1993.05.18
申请号 JP19910303806 申请日期 1991.10.24
申请人 NEC CORP 发明人 FUKUZAWA SHIGEKAZU
分类号 H04L7/027 主分类号 H04L7/027
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