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发明名称
INTEGRATED CIRCUIT LAYOUT PATTERN GENERATING DEVICE
摘要
申请公布号
JPH05120375(A)
申请公布日期
1993.05.18
申请号
JP19920003376
申请日期
1992.01.10
申请人
TOSHIBA CORP
发明人
KAWAKITA HIDEYUKI
分类号
H01L21/82;G06F17/50
主分类号
H01L21/82
代理机构
代理人
主权项
地址
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