System with modules using priority numbers related to interrupt vectors for bit-serial-arbitration on independent arbitration bus while CPU executing instructions

摘要

In a microcomputer including a CPU and a plurality of modules operatively connected through a main bus including address and data lines, a method of interrupting an operation including providing an interrupt request line and an arbitration bus, and arbitrating between modules and with the CPU on the arbitration bus so that no use of the main bus for arbitration or an interrupt acknowledge are required and the CPU can continue the operation as the arbitration proceeds.